1. Field of the Invention
The present invention relates to a reading circuit and method for a multilevel non-volatile memory.
2. Description of the Related Art
As is known, in floating-gate non-volatile memory cells, storage of a logic state is performed by programming the threshold voltage of the memory cells themselves through the definition of the amount of electrical charge stored in the floating-gate region.
Although they are based on the same principle, writing and reading of two-level memory cells, that is which are able to store only one bit, and of multilevel memory cells, that is which are able to store n bits, take place in different ways.
In particular, depending on the information stored, two-level memory cells are distinguished into erased memory cells (stored logic value xe2x80x9c1xe2x80x9d), in which no electric charge is stored in the floating-gate region, and written or programmed memory cells (stored logic value xe2x80x9c0xe2x80x9d), in which an electric charge sufficient to determine a considerable increase of the threshold voltage of the memory cells themselves is stored in the floating-gate region.
Reading of two-level memory cells is carried out by comparing an electric quantity correlated to the current flowing through the memory cells with a similar electric quantity correlated to the current flowing through a reference memory cell with a known content. In particular, to carry out reading of a two-level memory cell, a read voltage with a value between the threshold voltage of an erased memory cell and the threshold voltage of a written memory cell is supplied to the gate terminal of the memory cell itself, in such a way that, if the memory cell is written, the read voltage is lower than its threshold voltage, and thus no current flows in the memory cell; whereas, if the memory cell is erased, the read voltage is higher than its threshold voltage, and thus current flows in the memory cell.
In multilevel memory cells, storage of data of n bits, on the other hand, requires programming of threshold voltages which can assume 2n different values, with each of which is associated a corresponding datum of n bits, while reading of multilevel memory cells is carried out by comparing an electric quantity correlated to the current flowing through the memory cells themselves with 2n distinct reference intervals, with each of which is associated a corresponding datum of n bits, and then determining the datum associated with the interval of values within which said electric quantity is included.
FIG. 1 shows, as an example, a graph representing the current flowing in a two-bit memory cell and the reference currents which define the reference intervals used for reading the content of the memory cell.
In particular, in FIG. 1 the short-dashes line represents the current ICELL flowing in a memory cell, the content of which is composed of xe2x80x9c10xe2x80x9d bits continuous line represents the three reference currents IREF1, IREF2, IREF3 which define the four reference intervals. In FIG. 1 there are also indicated the two bits associated with each of the four reference intervals and, with a dash-dot line, the current flowing in a virgin cell which, as is known, is higher than the highest reference current (IREF3)
It is also known that reading of a memory cell is carried out by means of a reading circuit generally known as xe2x80x9csense amplifierxe2x80x9d (a term also used in this presentation) which, in addition to recognizing the logic state stored in the memory cell, also provides for the correct biasing of the drain terminal of the memory cell.
For reading multilevel memory cells, essentially two types of sense amplifiers are used: the so-called parallel or flash sense amplifiers, and the so-called synchronous serial dichotomic or successive approximation sense amplifiers.
FIG. 2 shows, as an example, the circuit architecture of a known parallel sense amplifier for reading a two-bit memory cell.
In particular, in parallel sense amplifiers reading of the content of the memory cell is carried out by comparing the cell current ICELL simultaneously with the three reference currents IREF1, IREF2, IREF3 using three distinct comparator stages 1 operating in parallel, one for each reference current, the outputs of which are connected to a decoding stage 2 which supplies the two bits stored in the memory cell to be read, depending on the logic level assumed by the outputs of the comparator stages.
FIG. 3 schematically represents the dichotomic algorithm implemented by the synchronous serial dichotomic sense amplifiers for reading the content of a two-bit memory cell, while FIG. 4 shows the circuit architecture of a known synchronous serial dichotomic sense amplifier.
In particular, as shown in FIG. 3, in synchronous serial dichotomic sense amplifiers reading of the content of the memory cell, in the example shown still composed of xe2x80x9c10xe2x80x9d bits, is carried out in two temporally successive steps, called dichotomic, one for each of the two bits to be read, in which, in the first dichotomic step, the cell current ICELL flowing in the memory cell is compared with the reference current IREF2, the value of which is intermediate between those assumed by the other reference currents, while in the second dichotomic step the cell current ICELL flowing in the memory cell is compared with the reference current IREF1 or IREF3, depending on the outcome of the comparison carried out in the first dichotomic step. In particular, if in the first dichotomic step the cell current ICELL is higher than the reference current IREF2, then in the second dichotomic step the cell current ICELL is compared with the reference current IREF3, while if in the first dichotomic step the cell current ICELL is lower than the reference current IREF2, then in the second dichotomic step the cell current ICELL is compared with the reference current IREF1.
In each dichotomic step one of the two bits is then decoded; in particular, in the first dichotomic step the most significant bit (MSB) is decoded, while in the second dichotomic step the least significant bit (LSB) is decoded.
As shown in FIG. 4, in synchronous serial dichotomic sense amplifiers reading of the content of the memory cell is carried out using a single comparator stage 3 which in the first dichotomic step compares the cell current ICELL with the reference current IREF2, while in the second dichotomic step it compares the cell current ICELL with the reference current IREF1 or IREF3, depending on the outcome of the comparison made in the first dichotomic step.
In particular, the selection of the reference current IREF1, IREF2 or IREF3 with which the cell current ICELL is compared is made with a multiplexer stage 4 controlled by a control circuit 5, which is also connected to two registers 6 or xe2x80x9clatchesxe2x80x9d in which the two read bits are stored.
Although widely used, parallel sense amplifiers and synchronous serial dichotomic sense amplifiers present certain inconveniences which do not allow all their good points to be adequately exploited.
First of all, both parallel sense amplifiers and synchronous serial dichotomic sense amplifiers present a high area occupation on silicon. In fact, parallel sense amplifiers require the provision of a comparator stage for each bit stored in the memory cells which, as is known, presents an area occupation that is not negligible, so that the use of this type of sense amplifiers is no longer advisable as the number of bits stored in the memory cells increases.
Although synchronous serial dichotomic sense amplifiers use only one comparator stage, they require the provision of registers for storing the bits read in each dichotomic step, of a multiplexer stage, and of a control stage. Moreover, this type of sense amplifier requires an accurate management of the various dichotomic steps, and so the circuit complexity of the control stage, and therefore its area occupation on silicon, increases significantly as the number of bits stored in the memory cells increases.
Furthermore, in synchronous serial dichotomic sense amplifiers the various dichotomic steps all present the same duration which is established a priori for the so-called worst case, that is to allow the reliable reading of a bit even when all the operating conditions that determine a slowing down of the reading (low supply voltage, high capacities to be load/unload, etc.) occur simultaneously, and are synchronized with each other, that is a dichotomic step starts after a pre-set time interval from the start of the previous dichotomic step, independently of the instant in which the first comparator stage has actually ended the comparison between the cell current ICELL and the reference current IREF2.
For these reasons, therefore, reading speed of synchronous serial dichotomic sense amplifiers is not very high, in particular the overall time necessary to read the content of a non-volatile memory cell assumes on average, in this type of sense amplifier, rather high values of around 20-25 ns which, in some applications, are not acceptable.
The disclosed embodiments of the present invention is to provide a reading circuit and a method for a multilevel non-volatile memory which allow a better combination, with respect to the known reading circuits described above, of the contrasting needs of reduced area occupation and high reading speed.
In accordance with one embodiment of the invention, a reading circuit for a non-volatile memory is provided that includes an asynchronous serial dichotomic reading circuit. Ideally, the asynchronous serial dichotomic reading circuit includes a first comparator receiving an electric quantity correlated to the current flowing in a multi-level memory and receiving an electric quantity correlated to a first reference current and outputting one of the bits stored in the multi-level memory cells; a selection circuit receiving the output from the first comparator and receiving an electric quantity correlated to a second reference current and an electric quantity correlated to a third reference current and outputting a signal selectively connectable to one of the first and second inputs depending on the logic level present on a selection input to the selection circuit; and a second comparator circuit receiving an electric quantity correlated to the current flowing in the multi-level memory cell and receiving at a second input the signal output from the selection circuit, and configured to supply another of the bits stored in the multi-level memory cell.
In accordance with another aspect of the foregoing embodiment, the selection circuit includes a first switch arranged between a first signal input and a signal output, the first switch having a control terminal connected to the selection input and a second switch arranged between a second signal input and a signal output and having a control terminal connected to the selection input through an inverter, the inverter having an input connected to the selection input and an output connected to the control terminal of the second switch.